1. Field
The present invention relates to a power supply circuit. Particularly, the present invention relates to a power supply circuit that employs a series regulator, and quickly responds to steep changes in load current so that changes in output voltage can be reduced.
2. Discussion of the Background
Some background power supply circuits use a series regulator. The series regulator has a relatively low efficiency due to a relatively large power consumption of a transistor when electric power is applied to a load that consumes a relatively large current. The series regulator, however, is capable of easily raising an output voltage and quickly responding to variations in an input voltage and a load fluctuation. In addition, the series regulator has a relatively high stability of the output voltage.
Referring to FIG. 1, a schematic circuit configuration of a background power supply circuit 100 that uses a series regulator is described.
In FIG. 1, the background power supply circuit 100 includes a reference voltage regulator 101, resistors Ra and Rb, an error amplifier 102 and an output driver transistor Me.
The reference voltage regulator 101 generates and outputs a given reference voltage VrA.
The resistors Ra and Rb detect and divide an output voltage Vout to generate and output a divided voltage VdA.
The error amplifier 102 includes n-channel metal oxide semiconductor (hereinafter referred to as “NMOS”) transistors Ma and Mb, p-channel metal oxide semiconductor (hereinafter referred to as “PMOS”) transistors Mc and Md, and a constant current source ia, and compares the divided voltage VdA and the reference voltage VrA. The PMOS transistors Mc and Md form a current mirror circuit.
The output driver transistor Me performs operations controlled by the error amplifier 102.
Operations of the background power supply circuit 100 are now described.
In a steady operation state, the error amplifier 102 controls the output driver transistor Me to make the divided voltage VdA equal to the reference voltage VrA, thereby stabilizing the output voltage Vout in a condition that a constant current is supplied to a load 110.
If the output current iout rapidly decreases in the steady operation state, the output voltage Vout rises. An increased amount of the output voltage Vout is divided by the resistors Ra and Rb to generate and output the divided voltage VdA. The divided voltage VdA is fed back to the NMOS transistor Mb of the error amplifier 102, which turns on the NMOS transistor Mb.
Since the PMOS transistors Mc and Md form a current mirror circuit, a total amount of current supplied from the PMOS transistors Mc and Md becomes larger than an amount of current supplied from the constant current source ia. Subsequently, a gate voltage of the output driver transistor Me becomes larger by an excess amount of current supplied from the PMOS transistors Mc and Md. This turns off the output driver transistor Me, with the result that the output voltage Vout falls.
Thus, the output driver transistor Me is controlled to adjust the divided voltage VdA to become equal to the reference voltage VrA so that the operation state may become steady, thereby stabilizing the output voltage Vout.
On the other hand, if the output current iout rapidly increases in the steady operation state, the output voltage Vout drops. The reduced amount of the output voltage Vout is divided by the resistors Ra and Rb to generate and output a divided voltage VdA. The divided voltage VdA is fed back to the NMOS transistor Mb of the error amplifier 102, which turns off the NMOS transistor Mb.
With the above-described operation, a total amount of current supplied from the PMOS transistors Mc and Md becomes smaller than the amount of current supplied from the constant current source ia. Since the gate voltage of the output driver transistor Me becomes smaller by a reduced amount of current supplied from the PMOS transistors Mc and Md, the output driver transistor Me is turned on to raise the output voltage Vout.
Thus, the output driver transistor Me is controlled to adjust the divided voltage VdA to become equal to the reference voltage VrA so that the operation state may become steady, thereby stabilizing the output voltage Vout.
In the power supply circuit 100 of FIG. 1, when the output current iout rapidly decreases, the PMOS transistor Mc is allowed to immediately charge an electric charge to be stored in a capacitor parasitic at a gate of the output driver transistor Me so as to stabilize the output voltage Vout.
However, when the output current iout rapidly increases, the output voltage Vout needs longer time to be stabilized, because the operation depends on the constant current source ia when discharging an electric charge stored in the capacitor parasitic at the gate of the output driver transistor Me.
To accelerate the stabilization of the output voltage Vout, a current supply capacity of the constant current source ia is increased. This allows a large amount of constant current to flow to the error amplifier 102, which increases consumption current of the power supply circuit 100.
Referring to FIG. 2, a schematic circuit configuration of a background power supply circuit 100a that uses a series regulator is described.
In FIG. 2, the background power supply circuit 100a includes a reference voltage regulator 111, resistors Rc and Rd, an error amplifier 112 and an output driver transistor Mj.
The reference voltage regulator 111 generates and outputs a given reference voltage VrB.
The resistors Rc and Rd detect and divide an output voltage Vout to generate and output a divided voltage VdB.
The error amplifier 112 includes PMOS transistors Mf and Mg, NMOS transistors Mh and Mi, and a constant current source ib, for comparing the divided voltage VdB and the reference voltage VrB. The NMOS transistors Mh and Mi form a current mirror circuit.
The output driver transistor Mj performs operations controlled by the error amplifier 112.
Operations of the background power supply circuit 100a are now described.
In a steady operation state, the error amplifier 112 controls the output driver transistor Mj to make the divided voltage VdB equal to the reference voltage VrB, thereby stabilizing the output voltage Vout in a condition that a constant current is supplied to a load 110.
If the output current iout rapidly increases in the steady operation state, the output voltage Vout falls. A reduced amount of the output voltage Vout is divided by the resistors Rc and Rd to generate and output the divided voltage VdB. The divided voltage VdB is fed back to the PMOS transistor Mg of the error amplifier 112, which turns on the PMOS transistor Mg.
Since the NMOS transistors Mh and Mi form the current mirror circuit, a total amount of current supplied from the NMOS transistors Mh and Mi becomes larger than an amount of current supplied from the constant current source ib. Subsequently, a gate voltage of the output driver transistor Mj becomes smaller by an excess amount of current supplied from the NMOS transistors Mh and Mi. This turns on the output driver transistor Mj, with the result that the output voltage Vout rises.
Thus, the output driver transistor Mj is controlled to adjust the divided voltage VdB to become equal to the reference voltage VrB so that the operation state may become steady, thereby stabilizing the output voltage Vout.
On the other hand, if the output current iout rapidly decreases in the steady operation state, the output voltage Vout rises. The increased amount of the output voltage Vout is divided by the resistors Rc and Rd to generate and output a divided voltage VdB. The divided voltage VdB is fed back to the PMOS transistor Mg of the error amplifier 112, which turns off the PMOS transistor Mg.
With the above-described operation, a total amount of current supplied from the NMOS transistors Mh and Mi becomes smaller than the amount of current supplied from the constant current source ib. A difference of amount between the output driver transistor Mj and the NMOS transistors Mh and Mi may be a trigger to turn off the output driver transistor Mj, with the result that the output voltage Vout falls.
Thus, the output driver transistor Mj is controlled to adjust the divided voltage VdB to become equal to the reference voltage VrB so that the operation state may become steady, thereby stabilizing the output voltage Vout.
In the power supply circuit 100a of FIG. 2, when the output current iout rapidly increases, the NMOS transistor Mh is allowed to immediately discharge an electric charge stored in a parasitic capacitor at a gate of the output driver transistor Mj so as to stabilize the output voltage Vout.
However, when the output current iout rapidly decreases, the output voltage Vout needs longer time to be stabilized, because the operation depends on the constant current source ib when charging an electric charge into the parasitic capacitor at the gate of the output driver transistor Mj.
To accelerate the stabilization of the output voltage Vout, a current supply capacity of the constant current source ib needs to be increased. This, however, allows a large amount of constant current to flow to the error amplifier 112, which increases consumption current of the power supply circuit 100a. 
Referring to FIG. 3, a schematic circuit configuration of a background power supply circuit 100b is described.
The background power supply circuit 100b of FIG. 3 uses a technique in which a constant voltage power source provided in the background power supply circuit 100b controls the output voltage to have a relatively fast speed of response.
In FIG. 3, the background power supply circuit 100b includes a current supply circuit 130, a current attraction circuit 140 and a feedback voltage power supply 150.
The current supply circuit 130 and the current attraction circuit 140 are connected at a voltage output terminal TO of the feedback voltage power supply 150.
The current supply circuit 130 includes a voltage source 131, a current source 132, a first diode 133 and a second diode 134.
The voltage source 131 generates an output voltage VL that is smaller than a working voltage of the voltage output terminal TO. The first diode 133 has a cathode connected to the voltage output terminal TO. The second diode 134 has a cathode connected to the voltage source 131. The current source 132 has a current output terminal that is connected to a connecting point of an anode of the first diode 133 and an anode of the second diode 134.
The current attraction circuit 140 includes a voltage source 141, a current source 142, a third diode 143 and a fourth diode 144. The voltage source 141 generates an output voltage VH that is larger than a working voltage of the voltage output terminal TO. The third diode 143 has an anode connected to the voltage output terminal TO. The fourth diode 144 has an anode connected to the voltage source 141. The current source 142 has a current output terminal that is connected to a connecting point of a cathode of the third diode 143 and a cathode of the fourth diode 144.
The background power supply circuit 100b generally maintains a relationship that an output voltage Vo of the voltage output terminal TO is smaller than the output voltage VH of the voltage source 131 and is larger than the output voltage VL of the voltage source 141. The relationship may be described in a relational expression of VH>Vo>VL. When the above-described relationship is maintained, an output current of the current source 132 flows to the voltage source 131, an output current of the current source 142 flows to the voltage source 141, and no current flows to the voltage output terminal TO.
When the output voltage Vo of the voltage output terminal TO decreases, the output voltage Vo becomes smaller than the output voltage VL. At this time, the current source 132 generates a current and supplies the current to the voltage output terminal TO to prevent the output voltage Vo from becoming smaller than the output voltage VL.
When the output voltage Vo of the voltage output terminal TO increases, the output voltage Vo becomes larger than the output voltage VH. At this time, the current source 142 draws a current from the voltage output terminal TO to prevent the output voltage Vo from becoming larger than the output voltage VH.
With the above-described operations, variations in an output voltage due to a delay in a response of the output voltage Vo may be prevented.
However, the background power supply circuits 100 and 100a as shown in FIGS. 1 and 2, respectively, cause a delay in a response with respect to a rapid change of the output current. When the power supply circuits 100 and 100a are used as a power source for driving a logic circuit such as a central processing unit (CPU), an output driver transistor having a large current supply capacity may be needed. If such output driver transistor is employed, the speed of response may be reduced as a gate capacity of the output driver transistor increases. A delay in a speed of response may cause substantial variations of an output voltage, which may result in a malfunction of the logic circuit serving as a load. To compensate the above-described drawback, the constant current source ia of FIG. 1 and the constant current source ib of FIG. 2 need to have a large electric current supply capacity, directing to an increase of the consumption current.
In FIG. 3, the background power supply circuit 100b controls the current sources 132 and 142 to maintain the relationship that the output voltage Vo of the voltage output terminal TO is smaller than the output voltage VH and is larger than the output voltage VL. While the relationship is maintained, the current sources 132 and 142 keep operating, consuming the current to increase an amount of consumption current, which substantially lowers a power supply efficiency.